|HODGES, D.A. & JACKSON, H.G.||ANALYSIS AND DESIGN OF DIGITAL INTEGRATED CIRCUITS
McGraw-Hill 2nd Edition 1988
|This edition is now out of print but still available in many college libraries. Its coverage is more extensive than necessary for this course. In general, the first half of the chapters cited in the syllabus contain the material that will be covered in lectures.|
|HODGES, D.A., JACKSON, H.G., & SALEH, R.A.||ANALYSIS AND DESIGN OF DIGITAL INTEGRATED CIRCUITS:
in deep submicron technology
McGraw-Hill 3rd Edition 2003
|This is an alternative to the reference listed above. The 3rd edition does not include some important material on NMOS circuits, diodes and bipolar devices and circuits. If this is used as the primary reference it will be necessary to supplement it with the following book.|
|SEDRA, A.S. & SMITH, K.C.||MICROELECTRONIC CIRCUITS
O.U.P., 5th Edition 2004
|This book is strongly recommended for supplementary reading. It covers a number of topics that have been left out of the 3rd edition of Hodges, Jackson and Saleh.|
|HOROWITZ, P. & HILL, W.||THE ART OF ELECTRONICS
C.U.P. 2nd edition 1989
|Topic||H & J
|H, J & S
|S & S
|1||Introduction to the course; the benefits and challenges of
Device miniaturisation and limitations.
Future prognosis for VLSI.
Logic gate definitions, transfer characteristics, noise margins, rise and fall times, delay times.
|Chapter 1||Chapter 1||10.1|
|2||MOS transistor operation. Threshold
I/V characteristics (demonstration). Ideal MOS equations.
Cross-sections of MOS devices.
MOS inverters with passive and active load devices.
Static analysis and examples.
|Chapters 2 & 3||Chapter 2||4.1
|3||The CMOS inverter: static analysis, voltage transfer
Detailed analysis of propagation delay, rise and fall time.
NAND & NOR gates.
|Chapter 3||Chapters 3, 4 & 5,
|4||Diodes: structure; forward and reverse
Minority carriers and charge storage. SPICE models.
Schottky barrier diodes.
|5||The bipolar transistor: structure; principles of operation;
The bipolar inverter: saturation and charge storage.
|Chapter 5||Appendix B
|6||Ebers-Moll models for bipolar devices.
Brief introduction to saturating bipolar logic families (DTL, TTL, STTL).
|Chapters 5, 6, 7||-||5.11
|7||Non-saturating logic: Emitter-coupled logic: operation and
CMOS Schmitt trigger.
BiCMOS logic: circuit operation, logic levels, estimates of propagation delay.
Comparison of BiCMOS with CMOS, ECL & other families.
Semiconductor memories: ROM and RAM architectures.
Static RAM cells.
Advantages and challenges of dynamic storage: a simple DRAM cell.
|Chapter 8||Chapter 8||11.1
Updated 03 January, 2007