Annotated copies of the presented lecture slides. To view these, you will need to download the file and use the Digital Class Viewer available here.
Regrettably the links formerly to useful articles (Scientific American and Institution of Electrical Engineers) no longer work and have had to be withdrawn until suitable alternatives appear.
This is a member of a suite of several applications produced some years ago by the Electronic Design Education Consortium to illustrate various devices, circuits, methods and design techniques in electronics. The module illustrating MOS transistor operation is used in the second of the E1 Digital Circuits lectures. Until very recently, licensing restrictions at the time prevented us from making this available as a downloadable archive.
However, this suite is now available on the web in archive form, provided courtesy of the Jorum Repository. Under the terms of the Jorum Repository, we have downloaded the most important elements as an archive and re-installed them on a CUED server.
If your computer is on a .cam.ac.uk subnet, you should have direct access; otherwise you will need your CUED PIN (in due course Raven password authentication will be introduced). You will need to download the Macromedia Authorware Player plugin for your browser (obtainable from http://www.adobe.com). This has worked fine with Microsoft's Internet Explorer, but with Firefox it is necessary to download the plug-in manually, then install it with the browser shut down.
Note that with the newest versions of Windows 7 and IE9, you may need to set up your Internet Security settings so that the site: www-g.eng.cam.ac.uk is added to your list of Intranet sites.
This applet is a slightly simplified version of the EDEC MOSFET model above. Try it! (But please note that it is a project under development, and may be withdrawn for update, etc).
These are a couple of examples of applets held in an archive at Dept of EE, SUNY, Buffalo USA. There is a longer list of other applets relating to materials, microelectronics, etc
The following two links no linger seem to work following a reorganisation at the Ecole Nationale Supérieure des Télécommunications web site. They have been left in the hope that the very useful applets to which they used to point might soon be found!
These two were found not to work reliably with all the latest IE4 and Netscape
However, Netscape Navigator 3, still available from the Netscape archive site has appeared to be suitable for them.
Examples Sheets - electronic versions for reference
Examples 1: MOS Circuits
Question 3 is well covered in Hodges and Jackson, 2nd edition. You will find that Questions 4 and 5 are closely linked to examples covered in H&J.
Questions 6, 8 and 9 show an alternative form of the S-H equations in which the factor 1/2 is embedded in the process gain constant itself. This is used in a number of references, though not in H+J. In these questions, just use the equations as given. Note that it's always been the practice in 3B2 exam questions on this material to state the S-H equations as given in the lecture notes.
These have been scanned in at 100 dpi and should be readable with a display of 800 x 600 pixels or greater. Click any of the hyperlinks below to see the corresponding part of the crib in a new browser window. Please do not send these images to the Department printers!
Acrobat PDF file
Question 1 | 2 | 3 | 3 cont | 4 | 4 cont | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 11 cont | 12 | 12 cont |
Acrobat PDF file
Question 1 | 2 | 2 cont | 3 | 3 cont | 4 | 5 | 6 | 6 cont (i) | 6 cont (ii) |
The files given below are sufficient to run the Spice simulator but they do not contain any graphical data; that is, the schematic presentation used in the lectures is not available. With pSpice versions 5, 6 and 7 it is possible to run the Spice Simulator alone without the graphical input; with pSpice 7.1 the simulation engine is called PSPICE.EXE. This allows you to select an input file, run the simulation and call up the PROBE plotter to plot graphs. No schematic entry required.
Note: Certain programs in the MicroSim pSpice family seem to have difficulty with long file names or paths like: 'C:\Program Files\msimev71\file.dat'. To avoid problems like this install pSpice in a directory like: C:\msimev71.
To use these files, select the text (displayed in Courier) starting at the first visible line (begins with '**'), down to the D in .END, and save it in a file e.g. DTRAN.CIR. Remember that Spice regards the first line as a comment. Run your installed version of pSpice on the saved file, and start PROBE to look at the results.
** DC and transient responses of pn and Schottky barrier
.DC LIN V_V2 0 5 0.1
.TRAN 2ns 100ns
D_D1 1 0 D1N4148
V_V1 2 0 PULSE 5 -5 10n 1n 1n 50n 100n
D_D2 3 0 DSchottky
R_R1 3 2 1k
R_R2 1 2 1k
.MODEL DSchottky D(IS=100E-10 N=1.03 RS=16 CJO=2PF TT=0NS BV=100 IBV=100E-15)
.MODEL D1N4148 D(Is=2.682n N=1.836 Rs=.5664 Ikf=44.17m Xti=3 Eg=1.11 Cjo=4p
+ M=.3333 Vj=.5 Fc=.5 Isr=1.565n Nr=2 Bv=100 Ibv=100u Tt=11.54n)
** CMOS inverter INV1598.CIR with 1pf load capacitance **
.DC LIN V_V2 0 5 0.1
.TRAN 1ns 100ns
M_M1 1 3 4 1 pmos L=3U W=20U
M_M2 4 3 0 0 nmos L=3U W=10U
C_C1 0 4 1p
V_V2 3 0 PULSE 0 5 10N 2N 2N 40N 100N
V_V1 1 0 DC 5
** Models for the nMOS and pMOS transistors
.model nmos NMOS(LEVEL=2 LD=0.225U TOX=275E-10 NSUB=2E16 VTO=0.87
+ UO=510 UEXP=0.22 UCRIT=24.3K DELTA=0.4 XJ=0.4U VMAX=54K
+ NEFF=4.0 RSH=65 NFS=0.E11 JS=2U CJ=160U CJSW=770P MJ=0.53
+ MJSW=0.53 PB=0.68 CGDO=250P CGSO=410P)
.model pmos PMOS(LEVEL=2 LD=0.2U TOX=275E-10 NSUB=5E16 VTO=-1.3
+ UO=210 UEXP=0.33 UCRIT=51K DELTA=0.4 XJ=0.5U VMAX=47K
+ NEFF=0.88 RSH=90 NFS=0.E11 JS=10U CJ=590U CJSW=710P MJ=0.46
+ MJSW=0.46 PB=0.78 CGDO=250P CGSO=410P)
Watch this space for more ..
Click the hot links in the tables below to see the results of simulation using pSpice, and note how much more effective the bipolar output stage is at driving the highly capacitive load.
With the steady improvement over the last few years in the performance obtainable from silicon-based MOS technology, it is tempting to assume that no alternative approaches are worth considering. This improvement has only been won at the expense of the most enormous investment of time and effort to refine the materials, manufacturing technology and design approaches.
Only ten years or so ago there was considerable debate over whether bipolar or MOS technologies held the greatest promise. Up till very recently, the fastest way of implementing logic circuits was by use of a non-saturating bipolar technology (so-called emitter-coupled logic). Fairchild Semiconductors is currently one of the largest manufacturers of ECL technology devices for military and aerospace applications - for example, their range of combinational logic gates. The fastest supercomputers and vector processors made heavy use of this kind of technology. The following articles (pdf files) contributed by Fairchild engineers show some important aspects of the use of ECL in demanding applications.
Some examples of ECL applications include:-
These are now part of the history of supercomputing, having been developed by in 1976 and 1985 respectively, by Seymour Cray of Cray Research, Inc. A major problem he had to surmount was the development of effective cooling systems to remove the vast amounts of heat developed by the ECL circuitry on which the design was based. Cray supercomputers are now based firmly on large-array parallel-processors and founded on CMOS technology.
This excerpt from the 5995M product specification clearly indicates the key role of high-speed ECL circuitry ..
"Logic chips on the 5995M processors use VLSI emitter coupled logic (ECL) to provide both high performance and high reliability. Main storage units incorporate static random access memory (SRAM) for very fast data access.
High-speed logic chips. The 5995M processors use two types of extremely fast VLSI logic chips. These devices have switching speeds of 70 and 80 picoseconds (ps).
Combined logic/RAM chips. VLSI logic circuits and high-speed random access memory (RAM) are combined on the same chip to reduce chip-to-chip communication times, resulting in faster instruction execution. This chip technology is used to implement buffer storage, microcode control storage, and register sets. Two types of chips are used: one with 64 kilobits (Kb) of RAM and one with 32 Kb of RAM. The logic circuits have a switching speed of 80 ps, and the RAM has an access time of 1.6 nanoseconds (ns).
High-speed SRAM chips. SRAM chips with an access time of 35 ns are used for main storage. SRAM chips allow main storage units to be compact and to provide fast and consistent access to data. They do not require data refreshing."
In the early 90's many commentators viewed CMOS as the most promising way forward, though even they recognised the problems of dynamic dissipation (where the repetitive charge and discharge of internal parasitic capacitances within gates gives rise to a frequency-dependent power dissipation) and the problem with MOS logic gates families of driving high capacitance loads. The advent of BiCMOS technologies over the last few years has offered an effective solution to this problem, and use of circuits based on this technology is becoming progressively more widespread.
Recent developments in bipolar technology are leading to even faster bipolar devices. Research at IBM has shown that fabricating bipolar devices from silicon with a small proportion of germanium added gives a significant speed enhancement. It's fascinating to note that the earliest transistors in the late 40s/early 50s were manufactured solely from germanium, but until this latest discovery germanium technology had been all but abandoned! The resultant HBT (Heterojunction Bipolar Transistor) is a supercharged device, operating at up to 120 GHz, many times faster than the best silicon-only devices that can now be made. IBM now have libraries of standard designs based upon it. There is considerable potential for using this approach in BiCMOS circuits, offering a further reduction in logic gate propagation delay.
Raw device speed is not the only frontier on which advances have to be made in the quest for the ultimate supercomputer. We are now entering an era of design for speed-of-light in computer systems. Light travels about 10 cm in one nanosecond, so that in a 500 MHz [2 ns] synchronous (i.e. controlled by a clock) computer design, we need to ensure that our signals have to travel no further than 20 cm. This means that the fastest computers in our future will have to be the smallest ...
High speed CMOS
IBM Research has announced breakthrough results in developing a new family of experimental high-speed computer circuits that run at test speeds up to five times faster than today's top chips. The new circuits employ an innovative design - called "Interlocked Pipelined CMOS" - to reach speeds of 3.3 - 4.5 billion cycles per second (3.3 - 4.5 GHz) using conventional silicon transistors, while dramatically reducing power consumption
Copper interconnect for faster logic
In 1997, fulfilling a dream of several decades, IBM introduced a technology that allows chip makers to use copper wires, rather than the traditional aluminium interconnects, to link transistors in chips. This advance gives IBM a significant lead in the race to create the next generation of semiconductors.
This set of pages has been accessed times since 7th Feb 2001.
Updated 26 March, 2013