4B7 VLSI Design, Technology and CAD

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Contents

Introduction

Link to local copy of Department Course Summary

The aim of module 4B7 (VLSI Design, Technology and CAD) is to describe the design, technology and manufacture of MOS integrated circuits and future nanoscale electron devices. It will provide a firm foundation for those wishing to pursue careers in applications or in research/development in the field of semiconductor devices/circuits.

LECTURES

VLSI Design and CAD of MOS Integrated Circuits (8L, Dr D.M. Holburn)

Integrated Devices and VLSI Technology (4L, Prof A Nathan)

Coursework

The Introductory lecture:

Other selected lecture material

Please click to open these in a new browser window.  The Adobe Acrobat plugin is required for the .pdf files.

Section and Title

MESP
course

4B7
(2014)

4B21
(2014)

Introduction - The Challenges of VLSI Design   YES  
Sections 1-3 - The MOS Transistor 
(includes links to interactive models)   
  YES  
Section    4 - The Transmission Gate   YES  
Section    5 - Deleted  
Section    6 - Design Rules (includes: Scaling in VLSI Design)   YES  
Section    7 - Circuit Extraction   YES  
Section    8 - Advanced Design Verification 
(MESP course only)
YES    
Section    9 - SPICE - Circuit Simulator 
(MESP course only)
YES    
Section  10 - Linear Circuit Design  YES    
Supplement - Integrated CMOS Voltage Reference YES
Section  12 - The logic abstraction   YES  
Section  13 - Deleted - in Prof Kelly/Prof Udrea's section  
Section  14 - I/O Pads and Pad Drivers   YES  
Section  15 - Energy Conservation in VLSI Designnewtiny.gif (931 bytes)   YES  
Section  16 - Test and Testability in VLSI 
(MESP course only)
YES    
Sections 17-19 - Deleted
Section  20 - Design Styles in VLSI 
(MESP course only)
YES    
4B7 Lectures given by Professor Arokia Nathan      
Lecture 1   YES  
Lecture 2   YES  
Lecture 3   YES  
Lecture 4   YES  
Lecture 5   YES  
4B21 Lectures given by Dr David Holburn      
Lecture 1 - Current and Voltage References and Applications     YES
Lecture 2 - Current and Voltage References – a Case Study     YES
Lecture 3 - Integrated Phase Locked Loops     YES

Examples

Lab Coursework

Electrical Characterisation of Ring Oscillator

SEM Examination of Ring Oscillator

Teaching Software

Electronic Design Education Consortium

edecbig.gif (10043 bytes)

Educational Java applets

This applet is a slightly simplified version of the EDEC MOSFET model above.  Try it!  (But please note that it is a project under development, and may be withdrawn for update, etc).

These are a couple of examples of applets held in an archive at Dept of EE, SUNY, Buffalo USA.  There is a longer list of other applets relating to materials, microelectronics, etc

The following two links no linger seem to work following a reorganisation at the Ecole Nationale Supérieure des Télécommunications web site.  They have been left in the hope that the very useful applets to which they used to point might soon be found!

These two were found not to work reliably with all the latest IE and Netscape Navigator browsers. 
However, Netscape Navigator 3 (also available from the Sunsite software archive at Imperial College) has appeared to be suitable for them.

Full custom design of a logic inverter

A Powerpoint animation depicting key stages in the full-custom design of a logic inverter was shown during a lecture - refer to section 6.0.  This represents a design carried out for an n-well process, in which the substrate is of p-type semiconductor, requiring an n-well to be implanted in which to fabricate the p-channel transistors.  You can view the Powerpoint animation on your browser:

The digitised 35 mm slides below are screen shots taken at a professional IC design terminal of a similar design.  The main difference is that the substrate is n-type, so a p-well is required in which to construct the n-channel transistors. Also shown is the green hatched active region, required to specify the sources, drains and channels with greater precision. The transistors are also oriented rather differently, and provision is made for the input and output to be brought in from above or below.

Click here for the set of images with descriptive text optimised for 800 x 600.

Click the thumbnail if you want to see the full-size image.

well.jpg (52129 bytes) P-well (diagonal brown shading).  The process illustrated is a p-well process.  This uses an n-type substrate in which the p-channel transistors will be fabricated directly.  The brown shaded region is implanted with p type dopants to form a p-well, in which the n-channel transistors can be fabricated.
welldiff.jpg (51841 bytes) P-well with active regions (green cross-hatching).  The active regions indicate zones where the transistor channels will lie. These regions are protected by a thin coat of silicon nitride while surrounding areas have a thick layer of field oxide grown upon them.  The smaller 'active' squares at extreme top and bottom will provide low-resistance connections to the substrate and the p-well, required to ensure proper isolation between devices.
wdpoly.jpg (35966 bytes) Polysilicon gate electrodes and polysilicon interconnect (red).  The single vertical strip of polysilicon crossing the two active regions provides the two gate electrodes and an electrical connection between them, and a route by means of which the input signal may be brought into the cell across the power rails (yet to be provided at top & bottom).  The polysilicon also helps delimit the regions implanted p+ and n+.
wdpimplant.jpg (31529 bytes) P+ and N+ implants (yellow and green).  These determine the positions of the source and drain in the corresponding devices.  N-channel transistors require n+ implants to form their drain and source, while p-devices require p+ implants.   Note that the polysilicon gate screens the channel region which does not receive these implants.
wdpicut.jpg (30657 bytes) Contact windows (black).  These indicate regions where an etch process cuts through the insulating layers, linking metal to semiconductor or metal to polysilicon.
wdpicm1.jpg (37446 bytes) Metal 1 (dark blue) furnishes the power rails (Vdd and Vss at top & bottom respectively, and a link between the two MOSFET drains, from which the output is coupled to points at the top and bottom of the cell by means of a vertical strip of polysilicon.

Useful Articles

Let me know if you discover any interesting articles that could be referenced here ..

Nanoscale CMOS - No Successor in Sight! (Powerpoint presentation) - Yuan Taur 
There is no credible candidate on the horizon that promises to supplant CMOS ULSI ..

Prospects of Si ULSI Devices for the Next Ten Years (.pdf file) - Yuan Taur, University of California (biographical details)
After three decades of continued growth, the microelectronic industry is facing unprecedented challenges in the next ten years. CMOS scaling, the engine that delivered higher density and performance and at the same time lower power and cost in the past, will encounter fundamental limiting factors and could be running out of steam below 50 nm dimensions ..

CMOS design near the limit of scaling (.pdf file) - Yuan Taur (2002) - biographical details
This paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length.

See how a silicon chip is made - Sematech (currently inactive - 2005)

How chips are made - Intel

International Technology Roadmap for Semiconductors (ITRS)
The International Technology Roadmap for Semiconductors (ITRS) is an assessment of semiconductor technology requirements. The objective of the ITRS is to ensure advancements in the performance of integrated circuits. This assessment, called roadmapping, is a cooperative effort of the global industry manufacturers and suppliers, government organizations, consortia, and universities. The ITRS identifies the technological challenges and needs facing the semiconductor industry over the next 15 years.  It represents a very dense set of data.  To start with, explore the Executive Summary for the current year.  As you find aspects that interest you, you can investigate the more detailed sections.

The Future of Integrated Circuits (includes archive documents from the mid-60's) for 2005
A roundup of progress in technology during the 60's and the emergence of Gordon Moore's Law for Intel microprocessor chips

http://researchweb.watson.ibm.com/journal/rd/462/wong.html

Beyond the conventional transistor
This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials.

Other Web Sites

newtiny.gif (931 bytes)Latest Developments


SEM images of microelectronic circuits

Click the thumbnail to see the full size image:-

partial.jpg (67497 bytes) CMOS 2 input NOR gate with passivation and upper metal layers removed (3 micron CMOS)
twonor.jpg (38720 bytes) A portion of a ring oscillator based on the CMOS 2-input NOR gate
divide.jpg (51280 bytes) A binary counter / frequency divider implemented on the same chip
ccdimage.jpg (30730 bytes) The view seen by a CCD camera placed in the SEM's specimen chamber.   Above, the curved conical feature is the magnetic objective lens. The electron beam is directed vertically down and is focussed on the specimen (a sliver of silicon wafer), fixed to a circular specimen stub.
dfm988.jpg (65769 bytes) Part of the IC studied in the SEM by last year's 4B7 group
dfm990.jpg (68652 bytes) The same area with a small cut machined using ion beam milling
dfm991.jpg (73746 bytes) A close-up of the machined cut.  In the full-size image you can clearly see the various semiconductor layers in section.
dfm999.jpg (45478 bytes) A mystery object ...
dfm1000.jpg (53758 bytes) A slightly different view ...
dfm1001.jpg (49573 bytes) And another ...
dfm1001.jpg (49573 bytes)dfm1000.jpg (53758 bytes)dfm999.jpg (45478 bytes) The collage may help you identify this everyday item ...

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Updated 16 November, 2014

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