Link to local copy of Department Course Summary
The aim of module 4B7 (VLSI Design, Technology and CAD) is to describe the design, technology and manufacture of MOS integrated circuits and future nanoscale electron devices. It will provide a firm foundation for those wishing to pursue careers in applications or in research/development in the field of semiconductor devices/circuits.
VLSI Design and CAD of MOS Integrated Circuits (6L, Dr D.M. Holburn)
Integrated Devices and VLSI Technology (6L, Prof F Udrea)
Please click to open these in a new browser window. The Adobe Acrobat plugin is required for the .pdf files.
|Section and Title||
|Introduction - The Challenges of VLSI Design||YES|
|Sections 1-3 - The MOS Transistor
(includes links to interactive models)
|Section 4 - The Transmission Gate||YES|
|Section 5 - Deleted|
|Section 6 - Design Rules (includes: Scaling in VLSI Design)||YES|
|Section 7 - Circuit Extraction||YES|
|Section 8 - Advanced Design Verification
(MESP course only)
|Section 9 - SPICE - Circuit Simulator
(MESP course only)
|Section 10 - Linear Circuit Design||YES|
|Supplement - Integrated CMOS Voltage Reference||YES|
|Section 12 - The logic abstraction||YES|
|Section 13 - Deleted - in Prof Kelly/Prof Udrea's section|
|Section 14 - I/O Pads and Pad Drivers||YES|
|Section 15 - Energy Conservation in VLSI Design||YES|
|Section 16 - Test and Testability in VLSI
(MESP course only)
|Sections 17-19 - Deleted|
|Section 20 - Design Styles in VLSI
(MESP course only)
Individual solutions: these have been scanned in at 100 dpi and should be readable with a display of 800 x 600 pixels or greater. Click any of the hyperlinks below to see the corresponding part of the crib in a new browser window. Please do not send these images to the Department printers!
This is a member of a suite of more than a hundred applications produced some years ago by the Electronic Design Education Consortium to illustrate various devices, circuits, methods and design techniques in electronics. The module illustrating MOS transistor operation was used in the second of the 4B7 Digital Circuits lectures. Unfortunately licensing restrictions at the time prevented us from making this available as a downloadable archive. This has now been resolved. Read on for details of how to access a web-based version.
Click on the EDEC button above for more details of the EDEC Consortium's activities (coming soon, when the link can be found).
This suite is now available on the web in archive form, provided courtesy of the Jorum Repository. While direct access to Jorum is restricted to staff only, even for browsing, under the terms of the Jorum Repository, it is permissible for registered members to download archives and host them for legitimate teaching purposes. It has now been downloaded as an archive and re-installed on a CUED server. The link given above provides a temporary interface to most of the functionality.
If your computer is on a .cam.ac.uk subnet, you should have direct access; otherwise you will need your CUED PIN (in due course Raven password authentication will be introduced). You will need to download the Macromedia Authorware Player plugin for your browser. This has worked fine with Microsoft's Internet Explorer, but with Firefox it is necessary to download the plug-in manually, then install it with the browser shut down..
If you tried before and were prevented from access by Jorum's access conditions, please try again 5 Feb 2009.
This applet is a slightly simplified version of the EDEC MOSFET model above. Try it! (But please note that it is a project under development, and may be withdrawn for update, etc).
These are a couple of examples of applets held in an archive at Dept of EE, SUNY, Buffalo USA. There is a longer list of other applets relating to materials, microelectronics, etc
The following two links no linger seem to work following a reorganisation at the Ecole Nationale Supérieure des Télécommunications web site. They have been left in the hope that the very useful applets to which they used to point might soon be found!
These two were found not to work reliably with all the latest IE and Netscape Navigator
However, Netscape Navigator 3 (also available from the Sunsite software archive at Imperial College) has appeared to be suitable for them.
A Powerpoint animation depicting key stages in the full-custom design of a logic inverter was shown during a lecture - refer to section 6.0. This represents a design carried out for an n-well process, in which the substrate is of p-type semiconductor, requiring an n-well to be implanted in which to fabricate the p-channel transistors. You can view the Powerpoint animation on your browser:
The digitised 35 mm slides below are screen shots taken at a professional IC design terminal of a similar design. The main difference is that the substrate is n-type, so a p-well is required in which to construct the n-channel transistors. Also shown is the green hatched active region, required to specify the sources, drains and channels with greater precision. The transistors are also oriented rather differently, and provision is made for the input and output to be brought in from above or below.
Click here for the set of images with descriptive text optimised for 800 x 600.
Click the thumbnail if you want to see the full-size image.
|P-well (diagonal brown shading). The process illustrated is a p-well process. This uses an n-type substrate in which the p-channel transistors will be fabricated directly. The brown shaded region is implanted with p type dopants to form a p-well, in which the n-channel transistors can be fabricated.|
|P-well with active regions (green cross-hatching). The active regions indicate zones where the transistor channels will lie. These regions are protected by a thin coat of silicon nitride while surrounding areas have a thick layer of field oxide grown upon them. The smaller 'active' squares at extreme top and bottom will provide low-resistance connections to the substrate and the p-well, required to ensure proper isolation between devices.|
|Polysilicon gate electrodes and polysilicon interconnect (red). The single vertical strip of polysilicon crossing the two active regions provides the two gate electrodes and an electrical connection between them, and a route by means of which the input signal may be brought into the cell across the power rails (yet to be provided at top & bottom). The polysilicon also helps delimit the regions implanted p+ and n+.|
|P+ and N+ implants (yellow and green). These determine the positions of the source and drain in the corresponding devices. N-channel transistors require n+ implants to form their drain and source, while p-devices require p+ implants. Note that the polysilicon gate screens the channel region which does not receive these implants.|
|Contact windows (black). These indicate regions where an etch process cuts through the insulating layers, linking metal to semiconductor or metal to polysilicon.|
|Metal 1 (dark blue) furnishes the power rails (Vdd and Vss at top & bottom respectively, and a link between the two MOSFET drains, from which the output is coupled to points at the top and bottom of the cell by means of a vertical strip of polysilicon.|
Let me know if you discover any interesting articles that could be referenced here ..
CMOS - No Successor in Sight! (Powerpoint presentation) - Yuan Taur
There is no credible candidate on the horizon that promises to supplant CMOS ULSI ..
of Si ULSI Devices for the Next Ten Years (.pdf file) - Yuan Taur,
University of California (biographical
After three decades of continued growth, the microelectronic industry is facing unprecedented challenges in the next ten years. CMOS scaling, the engine that delivered higher density and performance and at the same time lower power and cost in the past, will encounter fundamental limiting factors and could be running out of steam below 50 nm dimensions ..
design near the limit of scaling (.pdf file) - Yuan Taur (2002) - biographical
This paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length.
See how a silicon chip is made - Sematech (currently inactive - 2005)
How chips are made - Intel
Roadmap for Semiconductors (ITRS)
The International Technology Roadmap for Semiconductors (ITRS) is an assessment of semiconductor technology requirements. The objective of the ITRS is to ensure advancements in the performance of integrated circuits. This assessment, called roadmapping, is a cooperative effort of the global industry manufacturers and suppliers, government organizations, consortia, and universities. The ITRS identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. It represents a very dense set of data. To start with, explore the Executive Summary for the current year. As you find aspects that interest you, you can investigate the more detailed sections.
Future of Integrated Circuits (includes archive documents from the mid-60's)
A roundup of progress in technology during the 60's and the emergence of Gordon Moore's Law for Intel microprocessor chips
the conventional transistor
This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials.
|Engineers at the University of California, Berkeley, announced today (Monday, Nov. 22) the creation of a new type of semiconductor transistor so small that a single computer chip can hold 400 times more of the devices than ever before.|
|Using a revolutionary design, researchers at Bell Labs have produced the world's smallest transistor with equipment available in today's manufacturing facilities. This new design may help silicon chips continue their march toward smaller and smaller dimensions, and it has the potential added benefit of nearly doubling the processing speeds of some chips.|
|Recent developments in bipolar technology are leading to even faster bipolar devices. Research at IBM has shown that fabricating bipolar devices from silicon with a small proportion of germanium added gives a significant speed enhancement. It's fascinating to note that the earliest transistors in the late 40s/early 50s were manufactured solely from germanium, but until this latest discovery germanium technology had been all but abandoned! The resultant HBT (Heterojunction Bipolar Transistor) is a supercharged device, operating at up to 120 GHz, many times faster than the best silicon-only devices that can now be made.|
Click the thumbnail to see the full size image:-
|CMOS 2 input NOR gate with passivation and upper metal layers removed (3 micron CMOS)|
|A portion of a ring oscillator based on the CMOS 2-input NOR gate|
|A binary counter / frequency divider implemented on the same chip|
|The view seen by a CCD camera placed in the SEM's specimen chamber. Above, the curved conical feature is the magnetic objective lens. The electron beam is directed vertically down and is focussed on the specimen (a sliver of silicon wafer), fixed to a circular specimen stub.|
|Part of the IC studied in the SEM by last year's 4B7 group|
|The same area with a small cut machined using ion beam milling|
|A close-up of the machined cut. In the full-size image you can clearly see the various semiconductor layers in section.|
|A mystery object ...|
|A slightly different view ...|
|And another ...|
|The collage may help you identify this everyday item ...|
This set of pages has been accessed times since 7th Feb 2001.
Updated 26 March, 2013