Full custom design of a logic inverter
A set of images depicting key stages in the full-custom design of a logic inverter
(refer to section 6.0). These slides will be shown in lecture 6/7. The images
are digitised 35 mm slides.
- P-well with active areas
- P-well, active areas and polysilicon
- P-well, active areas, polysilicon and implants
- P-well, active areas, polysilicon, implants and contact cuts
- P-well, active areas, polysilicon, implants, contact cuts and metal 1
||[GO TO END]
P-well (diagonal brown
- The process illustrated is a p-well process.
- This uses an n-type substrate in which the p-channel transistors will be fabricated
- The brown shaded region is implanted with p type dopants to form a p-well, in which the
n-channel transistors can be fabricated.
P-well with active regions (green
- The active regions indicate zones where the transistor channels will lie.
- These regions are protected by a thin coat of silicon nitride while surrounding areas
have a thick layer of field oxide grown upon them.
- The smaller 'active' squares at extreme top and bottom will provide low-resistance
connections to the substrate and the p-well, required to ensure proper isolation between
Polysilicon gate electrodes and
polysilicon interconnect (red).
The single vertical strip of polysilicon crossing the two active regions provides:-
- the two gate electrodes
- an electrical connection between them, and
- a route by means of which the input signal may be brought into the cell across the power
rails (yet to be provided at top & bottom).
The polysilicon also helps delimit the regions implanted p+ and n+.
P+ and N+ implants (yellow and green).
- These determine the positions of the source and drain in the corresponding
- N-channel transistors require n+ implants to form their drain and source
- P-devices require p+ implants.
- Note that the polysilicon gate screens the channel region which does not receive these
Contact windows (black)
- These indicate regions where an etch process cuts through the insulating layers,
- metal to semiconductor or:
- metal to polysilicon.
Metal 1 (dark blue)
- Power rails (Vdd and Vss at top & bottom respectively, and:
- A link between the two MOSFET drains
The output is coupled from this link to points at top and bottom of the cell by means
of a vertical strip of polysilicon.