Module D7: VLSI Design, Technology, and CAD

14   I/O Pads and Pad Drivers

14.1 The Function of Pads and Pad Drivers

The circuitry on a chip has to connect with other circuits. These may be chips or display devices, transducers or electro-mechanical devices and the capacitance connected to the chip could be very large. In some cases the devices being driven will require or supply TTL signal levels, in others they may be liable to be short circuits, have high noise levels or be liable to discharge spikes of several kV. Each of these situations will require the imposition of circuitry to interface the chip to the external environment. Most IC designers avoid the problem of pad design and take pad drivers from standard libraries.

Physically, pads are the squares of metal, generally 100-150 m m square, that are connected to the pins of the package with bonding wires. The word pad is often used to also include the circuitry that is used to interface the CMOS logic within the IC (typically composed of near minimum-geometry transistors) to the outside world. At least two pads in each circuit will be used to connect the chip to the VDD and VSS power supply lines, while other pads will be used for input connections and output connections. Some pads may also be required to be bi-directional, (for use both with input signals and output signals). In such cases there is usually a control connection to determine the direction of signal transfer.

An important function for all pad driver circuitry is the protection of the chip circuitry against destruction due to overvoltage pulses or sustained overvoltages. These may be due to electrostatic discharges or due to faults on other circuitry that cause unexpectedly high voltages to be applied to the chip pins.

14.2 The Positioning of Pads and Associated Circuitry

Typical arrangements for pads and associated circuitry are shown in Figure 14.1.

 

Figure 15.1 Pads and associated circuitry

Bonding pads are normally positioned near to the chip edge, although there is often a VDD bus between the bonding pads and the chip boundary. Pad circuitry is almost invariably designed so that the various circuit blocks have standard physical sizes and provide regular spacing of the bond pads around the chip when the blocks are abutted.

It can be seen that continuous substantial aluminium interconnect is provided to form separate VDD and VSS buses around the ring of pads at the periphery of the circuit. These buses supply the current required by the pad drivers, and, in small designs, may also supply power to the inner circuitry. The necessary interconnections and crossovers are greatly facilitated by the use of double-layer metal. Pads and pad driver circuitry are a major consumer of chip area and any lack of compactness here will produce serious inefficiency in the total use of silicon area. Regular spacing of the bonding pads is normally required to facilitate the actual bonding process, the precise pitch and positioning being specified by the broker.

14.3 VDD and VSS Pads

Although it is possible to introduce overvoltages onto the chip via the supply connections, it is not feasible to provide any form of protection on these lines. They are, in any case, less sensitive to overvoltage than the signal connection.

The important considerations for the supply connections are the current requirements of the chip. There is an advantage in using multiple power supply pads, if the area is available, because this reduces noise levels. The 150 m m by 150 m m area typically used for the pad itself is likely will be adequate for the chip power requirements, but power buses of this width would take up too great a chip area. The necessary bus width must be calculated from the power requirements of the chip circuitry to:-

14.4 Input Pads

Input pads always contain overvoltage protection features, but can also contain inverting circuitry or Schmitt trigger circuitry if the input signals to be fed to the circuit are not known to be proper CMOS level signals.

An unprotected CMOS transistor typically has an input impedance greater than 1014 W . The capacitance of the gate is also very small, so sufficient electrostatic charge can easily be accumulated to produce a voltage high enough to cause failure of the input transistor. With modern processes, a voltage of only about 30 V or so is required to break down the thin gate oxide, although experiments have shown that failure is often caused by non-uniform current flow producing current densities that give thermal breakdown first. The action of walking across a synthetic carpet can give an individual a potential of 15 kV, so the first precaution is obviously to try to prevent electrostatic charge coming into contact with the chip pins. It is normally recommended that electrostatic kits with earthed mats and wrist straps are used for handling CMOS devices, but this is still not an adequate safeguard because so little charge is required.

The usual protection dircuit consists of a resistance and diode clamps, as shown in Figure 14.2.

Figure 14.2 Input protection circuit

 

D1 will turn on if the voltage at X rises significantly above VDD; similarly, D2 clamps the potential close to VSS if X is driven negative. The resistor R is normally a polysilicon track of about 1KW and this is used to limit the maximum current that can flow through the diodes (in the event of the diode turning on) to a non-destructive level. Modern designs tend to make use of a diffused resistor (for example, p-type diffusion in an n-well) even though this carries with it the risk of inducing latchup as a result of the injection of extra charge into the substrate under extreme conditions, e.g. voltage overshoot transients. As an alternative, a polysilicon resistor may be used (although it occupies more space); the thick field oxide isolation guards against the possibility of charge injection. An example of input pad layout is shown in Figure 14.3.

Figure 14.3 Input pad with a polysilicon resistor

The presence of the diodes reduces the input resistance of the circuit to ~1010 ohms. This is not likely to be important, but the effect of the protection structure on the speed of the circuit may be significant. The 1 kW resistor and the input capacitance of the first stage of the circuit will present an RC time-constant. If this time constant is unacceptable the value of the resistor can be reduced, but this will reduce the voltage capability of the protection circuit. Protection circuits should have a capability of about 2kV and 8 kV capability is possible with careful design without unreasonable degradation of the speed of the circuit.

14.5 Drivers for Output Pads

Output pads must be capable of providing relatively large currents for off-chip wiring, perhaps the inputs to several other devices. This must all be done with minimum expenditure of area and without slowing down signals to an unacceptable extent. In general, the faster a circuit is required to run, the higher the output current drive capability must be because charge must be delivered more rapidly to the device being driven. The driver circuit must act as a buffer so that changes in output loading do not affect the rest of the chip circuitry. Drivers are typically composed of logic inverters with high current drive capability. Often an even number of inverters may be connected in cascade if a non-inverting driver structure is required.

14.6 A Simple Pad Driver

The simplest type of design just uses a single inverter, but with very large transistors that have a high current-drive capability. A design of this type is shown in Figure 14.4.

Figure 14.4 A simple pad driver

The most notable features of this circuit are the numerous contacts to the well and the substrate and the unusual geometric arrangement of the transistors. The problems of latchup are greatest at I/O structures because the transistors used are large and the currents flowing are high. As a result, it is mandatory to use as many substrate and well contacts as possible, the normal guideline of ‘one per inverter’ being over-ridden here.

The geometric arrangement tries to ensure that the source fingers are perpendicular to the dominant direction of current flow. This is again a device to try to reduce the likelihood of latchup. There is also a relatively large spacing between the n and p transistors, which will also reduce the likelihood of latchup. Because the currents carried are large, a number of vias are used for the contacts between the two metal layers.

The sizing of the transistors depends on the capacitance of the load being driven and the required rise and fall times, t R and t F, for the output pulse. The relevant equations are:

t R = t F =

 

where C is the load capacitance, VDD is the power supply potential, and W and L represent the width and length respectively of the n- and p-type pad driver transistor channels.

These equations can be used to calculate the geometric ratios of the transistors for a certain load, but the channel length must still be decided. For minimum geometry logic gate structures it is conventional to use the smallest permissible channel length L. however, for large devices there may be process rule limitations that prevent minimum channel lengths being used.

14.7 More Complicated Pad Drivers

A significant disadvantage of the single stage inverter-driver is that it imposes a heavy capacitive load on the previous stage - which may be a minimum geometry device. The propagation delay t of this earlier stage will thus be increased, and may be estimated from the usual formula:-

t =

where C represents the capacitance at the input terminal of the pad driver, and all other parameters refer to the devices used in the earlier stage.

More generally, for a chain of cascaded inverters driven from some source resistance R0 and C0 respectively, and ultimately driving a pad (and external circuitry) of capacitance CL, we can write:-

T =

where T is the aggregate delay imposed by the cascade, and t i is the delay contributed by the ith stage. Although Ri is not a resistance in the strictest sense, it is a parameter with the dimensions of resistance, and is represented by a term of the form:-

Ri =

The expression for T can be rewritten:-

T =

where U is equivalent to Ri Ci, and is a constant parameter for a given MOS technology. Further, CM+1 = CL.

Intuition suggests that using gates of suitably graded dimensions, each one constructed from larger transistors than used in its predecessor, should minimise T.

An analytical approach calls for a formulation of the problem in terms of Lagrange multipliers; in this way it can be shown that T is minimised if t i = t i+1 = t 0. Thus there must be some constant g such that: Ci+1 = g Ci . We have

T = and CL =

Combining:-

T =

Optimising with respect to M we find g = e (the base of natural logarithms), and:

M+1 =

The minimum delay TMIN is:-

TMIN = M t0 =

A graph showing the variation of T with g takes the form of a shallow curve with its minimum at e. In practice, any value of g between 2 and 8 is acceptable.

The layout of a four-stage output pad driver of this type is shown in Figure 14.5. The interdigitated layout technique used for transistor sources and drains is elaborate, but leads to a compact design.

Figure 14.5 A four stage output pad driver

Another feature which can be seen here is the use of guard rings. These are rings of n+ diffusion tied to VDD around p+ diffusions (see Figure 14.6) and rings of p+ diffusion connected to VSS around n+ diffusions.

Figure 14.6 Guard rings

The purpose of these structures is to collect injected minority carriers and prevent them passing to other devices.

14.8 Inductive Effects

Many VLSI components have multiple outputs. Serious problems can arise when many outputs switch simultaneously, owing to transient voltage drops in the inductances inherent in the ground and power interconnect, and in the bond wire and pins on the chip package. These effects are modelled in the circuit below.

 

 

 

Transient voltages and currents in the power and ground circuit

Often the power and ground pins are located at the furthest corners of dual in-line packages. The inductance of the various power conductors lying between the I/O pad and the external pin ranges from 5 to 20 nH, depending on the specific dimensions. An output pad driver designed as outlined above will conduct large currents when switching typical off-chip loads (often up to 100pF capacitive). Assuming a package lead inductance L in the ground conductor, the inductive voltage drop is given by

Example. Typical numbers for a single output driver are a rise or fall time of 5 ns with a peak current of 50mA reached halfway through the switching time. With L = 10 nH, the peak value of Vg(t) is

Although this on its own is not enough to cause problems, consider a design with (say) 16 outputs. A bad situation would arise with one output low (and remaining low) while the other 15 outputs simultaneously switch from high to low. On the basis of the model described, the peak ground line voltage drop would be 15 0.2 = 3 V. The output of the sixteenth driver (which was supposed to remain low) will thus be raised in potential by 3 volts momentarily, producing a transient high logic level, quite possibly introducing a logic error. A corresponding effect arises in the VDD conductor.

Such errors can be reduced by:-