# Simulating Operational Amplifier circuits with pSpice

Besides basic devices (diodes, JFETs, MOSFETs etc) pSpice has a range of numerical models for more complex parts such as operational amplifiers.  We can use these to confirm some of the results deduced in lectures by analysis and calculation.

The Op-amp chosen for these simulations is the 741.  This has been a popular design for many years, and is available at very low cost from a number of different manufacturers.  The schematic below shows the main features of this device.

• The inverting input, non-inverting input and output terminals can be clearly seen.

• Terminals V+ and V- are the positive and negative power supplies to the chip.  Often left out of schematics, these are essential connections!

• Terminals OS1 and OS2 are fine adjustments to ensure the output is exactly at 0v when the input is at 0v.  It's often possible to ignore these in non-critical applications, like audio.

The schematic below shows Design Example 18.1.  The preferred values for the capacitors are shown.  The output terminal is loaded with a resistor R3 of 15k.   Since the output resistance of the circuit is reduced by negative feedback, the presence of this load does not cause any noticeable reduction in output.

Figure 1a - Schematic for Design Example 18.1 with Preferred capacitor values

The pSpice text input file is shown separately.

Shown below is the frequency response.  The axes as logarithmic: frequency is shown in convenient logarithmic decades, while gain is shown in decibels. The mid-band gain is expected to be x -10 (or 20 dB) and the -3 dB points (where the gain falls to 70.7% of the gain in mid-band) should be at 100 Hz and 5 kHz.  This can be confirmed from the graph.  However, notice how the actual gain does not quite attain the expected value of 20dB in mid-band.

Figure 1b - Frequency response for the design with preferred capacitor values

Just in case this is due to our use of 'preferred' values rather than the precise calculated values, the corrected circuit shown below in Fig. 2a is also simulated - results in Fig. 2b.  It can be seen that the gain does not reach 20dB in this case, either.

Figure 2a - Schematic for Design Example 18.1 with exact capacitor values

Figure 2b - Frequency response for the design with Exact capacitor values

The reason that the design gain of 20 dB is not reached in mid band is that the upper and lower cut-off points are rather too close together.  In the middle range of frequencies the 159nF capacitor  is still inserting a noticeable (though small) reactance in series with the input resistance.  The parallel capacitor of 318 pF has sufficient admittance to affect the feedback current.  We can confirm this by plotting the response with a larger value for C1 - say, 1590 nF instead of 159 nf - an increase by a factor 10.  This is shown below.

Figure 3 - Frequency response with C1 increased by a factor 10 to 1590 nF

Increasing C1 to 1590 nF pushes the lower -3dB point down by a factor 10, and there is an increased separation between the lower and upper cut-off (-3dB) frequencies.  We can now see that the gain achieved is now much closer to 20 dB over a substantial frequency range (from about 150 Hz to 300 Hz).

We can conclude from this that for there to be an identifiable 'mid-band' range of frequencies our design must have a sufficiently large separation between the lower and upper -3dB points.

Last updated: 28 September, 2005