Simulating a FET Amplifier with pSpice

Contents

Device characteristics - the data sheet

Before you begin a circuit design, it's useful to study the device characteristics for the device you're planning to use.

Every device has slightly different characteristics which must be accounted for in your circuit design.

The 2N3819 datasheet (PDF = portable document format) contains characteristics and graphs for a typical device, determined by the manufacturer from measurements on a large number of samples.  The pSpice simulator encapsulates device measurements such as these in a numerical model, which may comprise many parameters.

In the results and plots shown below, we are relying on a numerical model to predict how circuits will work. This is a remarkably effective approach, widely used by professional designers, but it is vital to remember:

The results are only as good as the model used

JFET I-V characteristics using pSpice

The circuit below entered into pSpice will let us plot out I-V characteristics of the device J1 corresponding to pSpice's numerical model.  It's important to remember, this is a prediction of how a typical device will respond, and not a measurement as such.

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I-V Plot circuit for a 2N3819 JFET

The data actually entered into pSpice is text-based.  The schematic is just for the convenience of a human designer.  Fortunately, it is fairly easy to convert a schematic diagram into data that pSpice can accept.  Here's the input that corresponds to the schematic above; it instructs pSpice to plot the drain current in J1 as a function of VDD (the drain voltage) and VG (the gate voltage) as these are varied between prescribed limits.

* Jfet DC nest sweep
V1  1 0       DC 0
V2  2 0       DC 0

J1  2 1 0 J2N3819

.model J2N3819 NJF(Beta=1.304m Rd=1 Rs=1 Lambda=2.25m Vto=-3
+ Is=33.57f Cgd=1.6p Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1)

* Nest DC sweep
.DC V2 0 20 .1 V1 -2.6 0 0.2
.END

Shown below is the transfer characteristic ID vs. VGS plot for the 2N3819 n-channel JFET.  

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Figure 1a - The Spice ID vs. VGS plot for a 2N3819 JFET

pl38190.png (6286 bytes)

The topmost curve is for a gate-source voltage of 0V
Successive curves have a gate-source step voltage of -0.5V

The DC Operating Point and Load Line

Now that we have the characteristic I-V plot for the device, we can choose a DC operating point Q for the device. There are a number of factors to consider when picking the operating point for our circuit.  These were covered in Lectures 7-8.

Choosing the Operating Point 

First of all, we want the amplifier to work in a linear region to minimise the amount of signal distortion.  The optimum region for the JFET is in the region where the drain current ID is essentially constant, the so-called constant current region.

We must avoid the region where VGS > 0, and where VDS exceeds the manufacturer's limit, and we must take care that the product: ID x VDS does not exceed the maximum safe power limit, to avoid overheating.  Typically, we will choose an operating point Q that lies near the centroid of the safe region.

Another concern of the circuit designer is power consumption. Since the circuit consumes a certain amount of power even if no signal is connected to the input, typically a designer will wish to minimise the power consumption. This can be achieved by using as small a drain current as necessary to do the job that the amplifier needs to do.

Choosing VDS to maximise the range of output signals

We also want to maximise the output range of our amplifier. If our operating point Q point is too close to earth potential, or to the supply voltage, the signal will clip (that is, it will be limited in amplitude by the power supply) much sooner then if it were farther away from those two voltages. For this reason, the device is typically set up to operate at midpoint bias. This means that the JFET is biased so that the drain-source voltage is approximately halfway between the supply voltage and earth potential.

In this example, we've chosen an operating point with a drain current of approximately 3 mA and a drain-source voltage of approximately 10 V.

Once the operating point has been chosen, the only other parameter of the circuit is the supply voltage, which was probably already known, and likely a factor in the selection of the operating point. We will use a supply voltage of 20 V.

Constructing the Load Line

The next step is to draw a line from the X intercept at the supply voltage point, through the operating point Q, all the way to the Y axis. This is the DC load line, which governs the operation of the circuit, and determines the value we choose for the drain resistor RD.  It has slope -RD.

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Figure 2 - DC Load Line for Amplifier

Selecting the components

The preliminary work is now complete, and we are ready to begin selecting the components necessary to complete the circuit. 

To bias the gate at the proper voltage (-1.5V according to the I-V plot), we need to provide a 1.5 V bias battery. 

The operating point has been chosen as VDS = 10V and ID = 3 mA.  This means that the remaining 10 volts has to be dropped across the drain resistor RD, while a drain current of 3 mA flows. This gives RD = 10/3 kohms or 3300 ohms.  The design of the circuit is now complete.

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Figure 3  Circuit design details for JFET Common Source Amplifier

Response to a Small Signal - 100 Hz, 0.25 V p-p sine wave

Applying a sine wave of 0.25 V peak, or 0.5 V peak-to-peak at the input gives us the following output signal as a function of time, or transient response.

pl3819b.png (7091 bytes)

Figure 3 - Transient response of Fixed-bias JFET Amplifier

Hence the voltage gain is Vout/Vin = -5.8/0.5 = -11.6 approximately.

The self-biased JFET amplifier

sc3819s.png (9061 bytes)

The self-biassed design allows the bias battery to be eliminated, saving an expensive and bulky battery, at the cost of only one additional resistor RS.  From above, to achieve the required operating point, Q, requires the gate electrode to be biased at -1.5 volts relative to the source electrode.  With self-bias, we keep the gate itself at 0 volts, and raise the potential on the source electrode to +1.5 volts - which amounts to the same thing.  

RG holds the gate at earth potential, or 0 volts, since negligible DC current flows into the gate electrode.

The voltage drop across RS is given by: ID x RS.  Since ID is fixed at 3 mA for the chosen operating point Q, we choose 500 ohms for RS; the closest convenient preferred value is 470 ohms.  

The graph below shows the output predicted by pSpice for the self-biassed circuit.  Note that the vertical scale for the output (lower plot) goes from 8V to 12V.

pl3819s.png (8492 bytes)

Taking into account the the different scaling, the output is now considerably lower than for the battery-biased circuit, with the same input applied.  The gain has in fact been reduced, to about -2.1/0.5 ~ -4, compared with over 11 for the battery-biased circuit.  Why is this?

Because of the presence of the source resistor RS, there is now a fluctuating signal appearing on the source electrode, as the drain current varies.  Consideration of Kirchhoff's voltage law shows that the gate signal voltage vgs is actually reduced below 0.5 V p-p by presence of this signal on the source, and the output is lower as a result.  This is an example of negative feedback.  Here it is producing an undesired reduction in circuit gain, but properly applied in the right circumstances, negative feedback is an exceedingly powerful technique of immense value in linear circuit design.

The effect of the Bypass Capacitor

Fortunately, there is an easy solution to this - see the schematic diagram below.  If we connect a bypass capacitor C3 of sufficiently large capacitance in parallel with RS, a bypass path is provided for signal currents to flow directly to earth, rather than through RS; then the full input signal appears between the gate and source, restoring the gain to the expected value.  The crucial service performed by C3 is effectively to short-circuit the source resistor RS for signal frequencies only.  

However, because no DC current flows through a capacitor, the steady source voltage needed to establish the gate bias (to achieve the operating point Q) is unaffected.  

For the moment, we will sidestep the issue of how to select a 'sufficiently large' value for C3, and we will assume that a value of 100 mF will be satisfactory.

Here is a link to the pSpice circuit (schematic) file that describes this design.

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The sine wave response is as shown below, and at the frequency in use, 100 Hz,  it can be seen that the gain has been restored to about -11.5.  At this frequency it is apparent that the bypass capacitor C3 (100 uF) is adequate.  However, if the frequency were reduced this might not be the case, since capacitive reactance is inversely proportional to frequency.

Choosing a suitable bypass capacitor

The following simulation run shows how pSpice can be used to show the effect of varying C3, to establish how sensitive is the design's performance to the choice of value.  pSpice allows the designer to experiment with virtually any parameter or combinations of these, offering great potential for 'what-if' experiments.  

The circuit schematic is almost identical to the previous one, but the annotation {Cval} in place of  100 uF) indicates that on this run, C3 will be varied over a range of values.

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To show the results, we could apply a standard sine wave signal at the input and study the amplitude of the resultant output sine wave.  However, this is rather tedious, and pSpice is capable of interpreting the results for us, actually determining the amplitude of the output.

Hence, to see the effect of varying C3 we have pSpice plot output voltage amplitude versus frequency to give a set of frequency response graphs, one for each C3 value.

pl3819p.png (8951 bytes)

For this set of results, the input was set to 1 volt p-p, so the vertical scale (which represents the p-p output voltage at the drain) is numerically equal to the gain.  You can see that the transition between low gain (about -4) to high gain (about -11.8) happens at a different range of frequencies, according to the value of the bypass capacitance C3.   

The plots have been labelled to show the value of bypass capacitor used.  Note that the frequency scale is logarithmic. 


Last updated: 29 November, 2005