Part IIA CBT Project on VLSI Design
VLSI Design/Mentor Resource Page
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Page last updated 20:15 on Monday, 15 May 2006
Newsflash 
on Monday, 15 May 2006
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Your Final Report!
The deadline for the Final Interim Report for the project is Saturday
10th June
5 pm.
Things you should consider when deciding what to include in the
report are mentioned in the FAQ on the Bulletin
Board
Handing in your report
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Colour Printing for ICgraph - all change in 2006!
We have had no real success in making the standard methods for printing
out cells work in colour. This is a real minefield in Mentor and has
caused much gnashing of teeth in previous years as well. However, we
do now have a work-around, which has required us to set up an entirely new
link to the Department's print infrastructure. The approach required
is therefore quite different from before - but that is not unusual in
Mentor, which often offers two or three different ways to accomplish any
given task. Unfortunately, mgcplot cannot be used, and
the new method does not allow for easy image preview before printing, so
a little more care is needed - please do not be extravagant in your usage. It is also available only for colour
plots, and for ICgraph - for other tools the standard recipes for monochrome
plots, as detailed in the
Project Guide, still work fine.
To generate a colour check plot from ICgraph proceed as follows:
- With the design you wish open in ICgraph and on the screen with its window
activated, give the command:
File -> Print -> HotPlot.
- The HotPlot dialogue should appear. Under Plot
Handling select Use Formatter.
- Click the Set Formatter Options button, and in the Formatter
Only Options dialogue, use the Browser button by the top
text box to find and select the Plotcap file, called Plotcap,
which is to be found in your cbt directory. OK the
dialogue box.
- Click the Select Printer button, and select the only
available printer "Postscript" that appears in the Select
Hotplot Printer dialogue. OK the dialogue box.
- Click the Browse button next to the Setup File text
box, and use the Select Hotplot Setup File browser to locate
and select the file setup.p which is also to be found in your cbt
directory. OK the dialogue box.
- Click the Select Layers button, and in the Print Layers
dialogue, with the shift key pressed, select the layers 1 to 17, from n-well
down to n-window. OK the dialogue box.
- Click the Maximize button, followed by the Compute Plot
Size button, then the Scale by
Width/Length button.
- Click the Set Plot Attributes button and in the Hotplot
Plot Attributes dialogue that appears, check that Send Plot to
Printer is checked. OK the Hotplot Plot Attributes
dialogue, and OK the Hotplot dialogue. Your plot should
be sent to the Colour Laserjet, cljmr1, in the Operators'
area.
- You may need to experiment with the scaling and rotation parameters
to get the best fit of your design to the printed sheet.
- Note: you can uncheck Send Plot to Printer to have
HotPlot create a Postscript file in your cbt directory;
typically it will be called rinaxxxx, if your design is called ring_flat
or ring_hier, where xxxx is a numeric string; you can preview
this using gv rinaxxxx. This exercise is strongly
recommended - zooming in to study key elements (for example, in the
ring oscillator, or in an input or output pad driver) is far more
practicable on a screen-based image, and will throw much light on the
structure.
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Schedule for Week 1
You should aim to complete Lab Guide 1, which introduces the Mentor Falcon Framework
and the on-line Help System, as soon as possible.
At the first opportunity read those sections of the project manual covering
You are likely to need most of Tuesday afternoon (and possibly some unscheduled time)
to complete Lab Guide 2 - Functional Simulation with
ModelSim.
You should aim to complete Lab Guide 3 - Transistor
Schematics on Friday morning.
Both Lab 2 and Lab 3 will produce important results which you will need when compiling
your First Interim Report.
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VHDL Command syntax
An appendix summarising the syntax for VHDL commands is attached as pages 46-50 at the rear of the section: Hardware
Description Language VHDL.
This may help you in Lab Guide 2 - Functional Simulation
with ModelSim. You can see an html
version of the command syntax here. There are sample
VHDL files you can inspect here. Note: these are
indicative only and will require adaptation to suit your
design.
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Correction to Lab Guide and other documents
Please note the following amendments-
Lab guide
Quick reference leaflet:
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This year for the VLSI project we shall make use of the twnXX graphics
workstations. This is a major bonus since these workstations offer greater
comfort and clearer screens, with large-format TFT displays
attached. Please note the workstations are available to us as follows:-
- as priority users during the scheduled project periods on Tuesdays 9.00 - 11.00,
13.30 - 17.30 and Fridays 11.00 - 13.00
- at other times you can use them if they are not being used by other priority
users.
Tuesday afternoon sessions are scheduled to run from 1.30 pm to 5.30 pm, and we are
priority users of the twns during that period. If you have
difficulty finding a seat or are being harassed by others intent on turfing you off during
this period, please consult a demonstrator, or if one is not available, the
Computer Operators may be
able to assist.
If a twnXX is not available you will need to login from one of the
other Teaching System workstations - see the handouts and supplementary information below.
The twnXX workstations are high performance PCs running Windows
XP Mentor itself runs on a Unix host.
We shall be using the X-win32 X server running on the PCs to
access Mentor on tw300 and tw600.
Monitoring this page
You are strongly advised to monitor this page, which will be updated regularly to show
latest information, advice, etc. Please also monitor the Project Intranet,
recently introduced. You are welcome to access either of these from college or
wherever is convenient.
You can monitor these pages while logged in on the Teaching System as a Mentor
user. However, it appears that Netscape (when run on the Teaching System) sometimes
interacts adversely with some graphical displays, giving (for example) purple text on a
black background.
To circumvent this, note that the PCs are equipped with Firefox and Internet
Explorer browsers which you
can run locally (on the PC rather than on the Teaching System). This eliminates the
problem.
Shared Mentor Workspaces
This project makes use of shared workspaces, shared between members of the
groups of 2 formed at the start of the first session. Although you will
login using your own identifier, all your project design materials will be held
in the shared workspace.
Users often receive an email from the Computer Operators (text in italics below) to
explain some of the features of shared workspaces.
The recommendations in the email provide some useful refinements, but are not strictly essential for our use on the Mentor project.
In case this message is not automatically sent this year, the gist is presented below.
A shared group directory has been set up for you called mentorX (where X is a number 2-9). In
order to access this shared filespace you may wish to create a link between your own file space and the shared directory. On the Unix Teaching System in the DPO type:
ln -s /usersG/ptiivlsi/mentorX ~/mentorX where
X is your group no.
The instructions in the Project Guide tell you how to change directory at the start of every session using:-
cd /usersG/ptiivlsi/mentorX
If you follow the advice above with the ln command, this simplifies to typing (while in your home directory):
cd mentorX
It is important that the files created in the shared space have the correct permissions, and this involves using the umask command.
Before changing directory (command cd) on the Unix Teaching System into the shared space type: umask 007 so that any files created or
edited in your group are readable and writable by everyone in the group. ...... The umask command needs to be typed EVERY time you login to the Unix Teaching System and wish to share files in this group.
For this project problems will arise if you create files that are
editable only by the person who created it: all data needs to be shared
between both members of each pair. The mentor_start_env script which
we recommend you to use contains the recommended umask command. Its
effect persists throughout the Mentor session, but the setting is restored to the normal value
on exit. Please note the following:
- You should not normally need to use the umask command, unless you want to create or modify shared files outside Mentor;
- NB modifying CAD files outside Mentor is risky, and not advised!
When you finish your Group session, log out. This will have the effect of resetting the default umask for the files in your own
filespace. If you have any problems get help from the Operators whose office is at the far end of the DPO by the printers.
operators@eng.cam.ac.uk
Logging in
As per the printed notes. Log in to Windows XP by first hitting
<Ctrl><Alt><Del>, then entering your own UID and password.
Start up the browser pointing to this page(!) or the Project Intranet.
Click the Mentor icon, which actually just starts the X-win32
application so you can login to the Teaching System.
Login, using your normal UID and password.
You will be presented with a choice of servers on login. Normally you should choose the
one allocated to you, then give commands as advised in the notes:-
. mentor_start_env (NB the dot-space at the
beginning of the line)
Pause while the window manager fvwm etc starts up
mentor
Note the availablity of a popup menu (click over fvwm desktop with RH
mouse button) which lets you run a couple of useful Mentor utilities.
Logging out
Once you have closed all Mentor application windows (Design Manager last of all) and
the associated transcript windows, left click on the fvwm desktop and
give the command: Exit fvwm > Yes, really quit. This should
clear the desktop and invoke the server menu.
Next, exit from the Xwin32 utility by clicking on its 
button at top right.
Finally, log out of Windows XP by clicking 
and selecting the option: Shut down ..
followed by Logon as different user.
See below for slight variations on this if you login from other workstations (i.e.
outside the scheduled project times).
The following procedure, which assumes you propose to login to your account via
workstation tw212 in the DPO:-
Login in the normal way to tw212 as yourself.
An xterm window should appear. Don't start a Window Manager at this stage.
In the xterm window give the command
| xon tw3
-or-
xon tw6 |
(according to the server required) |
You may be required to give your password at this stage.
Now give the commands:
| . mentor_start_env |
(note the 'dot-space' at the start of the line.
This is important!) |
| mentor |
(you may need to use a different script if your terminal has
an unusual keyboard configuration, e.g HP |
Then continue to work as normal, ignoring the first (login) window until you actually
want to logout.
If you have any queries about the project, you can email them to:-
mentor1@eng.cam.ac.uk
Using this address ensures that the message will be copied to all demonstrators.
Important: please make an early start on this experiment.
There is not enough equipment for everyone to do the experiment at the same time.
The experiment relating to Electrical Testing of the Ring Oscillator will be set up in
the E & I E Teaching Lab and will be available from Friday 19th May. The Lab
Guide for this in included at the end of your Project Manual, but there will
also be a few
copies in the E & I E T L. A demonstrator will be available for this part of the
project during scheduled sessions (only), when there will be a sign-up sheet, but
it may not be possible for the demonstrators to be present in the E & I E T L full
time. You can carry out the experiment, with your partner, at any convenient time
(during laboratory hours) from Friday 19th onwards, and you should include the
material in your Final Report.
The deadline for the first interim report for the project is on Monday 22nd
May.
A summary information about the expected content of the report is given below.
- The preliminary design specification for the ring_oscillator ring oscillator
IC (Mentor schematic not expected at this stage).
- Results of the initial exercises in Design of Logic Gates in CMOS, page
24
- Procedures for model development, compilation and simulation using ModelSim
- 'What if' experiments carried out to investigate effect of different gate delays
- Behaviour of the simulated ring oscillator with a short double-pulse applied
- Operation of the 4-bit counter, comparator, programmable counter
- You should include the results of the work in Lab Guide 3, Section I - which involves
printing out a schematic
- Then carry out the exercises in Lab Guide 3, Section II; the results are needed in the
report
- Finally, follow the instructions in Lab Guide 3, Section III, print out the updated
schematic and include it in the report
- Please do not include material from Lab Guide 4 and 5, nor results from
the Ring Oscillator Electrical Characterisation experiment
Note that this is just the bare bones; a good report will also give attention to
overviews and aims of work carried out as well as conclusions drawn and any implications
for future work. The report should be 2 written sides maximum, plus appendices which may
include calculations, printed schematics, listings etc.
Handing in your report
- Please hand your completed report by 5 pm on Monday 22nd May. You should post it
in the box used earlier this year for Part IIA Long Experiments, on the landing outside
the E & I E T L.
- Your report should have a completed Feedback Form attached. These were distributed
in the first session, but the demonstrators (DPO) and Mr Furber (E&IETL) will
have a few copies.
- It will be our aim to get all first reports marked and back to you by the session on
Friday 26th May.
You may start Lab Guides 4 and 5 as soon as you feel you have completed Lab Guides 1, 2
and 3 and gathered the necessary material for the first report.
The deadline for the Second Interim Report for the project is Monday 29th May. The
report should be 2 sides maximum, plus any printed schematics, listings etc.
Basically, this report should cover the material gathered in labs 4 and 5. These
are the main points:-
- development and creation of the ring_oscillator schematic and symbol and the ring
schematic
- procedures for viewpoint creation and simulation using QuickSim II
- characteristics of the simulated behaviour of the 2-input NOR gate and input/output pads
- timing models available in QuickSim II
- further simulation (using QuickSim II) of ring oscillator and programmable
counter with all ancillary reset and enable functions
Note that this is just the bare bones; a good report will also contain:-
- consideration of the relative advantages and disadvantages of the different approaches
to simulation
- overviews and aims of work carried out
- conclusions drawn and any implications for future work.
Please note also the following:-
- Work based on Lab Guides 6, 7 and 8 and associated exercises should be covered in the
final report
- The ring oscillator experiment write-up should be included in the final report, not
the interim report.
Handing in your report
- Please hand your completed report to Mr Furber by 5 pm on Monday 29th May. You
should post it in the box used earlier this year for Part IIA Long Experiments.
- Your report must have a completed Feedback Form attached. Spare
copies are available from the demonstrators in the DPO, and from Mr Furber in the E & I E T
L.
- It will be our aim to get second interim reports marked and back to you within a week.
The deadline for the Final Interim Report for the project is Saturday
10th June
5 pm. The report should be 10 sides maximum, plus any appendices (printed schematics,
listings etc).
A good report is likely to contain references to most if not all of the following.
Please note that the list is not intended to be definitive, and there is no
significance to the order in which the items are listed.
- Report on electrical testing of supplied ring oscillator circuits
- Stick diagram for 2 input NOR
- Effectiveness of VHDL modelling as a guide to design
- Summary of modifications to supplied nor2 layout
- Correction of any design rule violations
- Estimation of parasitic capacitances and their importance in predicting delay
- Optimisation of NOR gate layout to enhance speed
- Results from LVS verification procedure and comments
- Extracted parasitic capacitances and their significance
- Use of Accusim to explore behaviour of nor2 gate and constrain layout design
- Implications for QuickHDL simulation results
- IC layout - semi custom - efficiency achieved by various means (flattened and
hierarchical)
- Benefits of compaction and via minimisation
- Advantages/disadvantages of flattened/hierarchical approach
- Life cycle of typical CMOS IC design
- Comments on suitability of tools
- Accuracy of simulation results
Be sure to see also the Third
Year Project Guide
Please note also the following:-
- You must enclose both previous marked interim reports,
securely fastened to your final report.
Handing in your report
- Note that this is different from the procedure used for first/second reports.
- Please hand in your report on Saturday 10th June, to Dr
Robertson or his deputy in the
Entrance Lobby, CUED, between 3 pm and 5 pm.
IMPORTANT - Do not try to hand in your report at any other place in the
Department.
- Your report must have a completed Feedback Form attached. Copies
should be available at the Enquiries Office on Saturday.
Hints and tips
Modelling the sequence generator in HDL
You will need to determine how to create a shift register of 6 elements or
greater, then consider how to connect the appropriate shift register outputs to the inputs of
the XNOR gate. We would like the maximum length sequence available
from a 6 bit register.
You can read about possible configurations for the shift register in The Art of
Electronics by Horowitz & Hill, C.U.P., p. 656-7 in the 2nd Edition.
For a shift register of m bits with feedback taken from outputs n and
m, the maximum length sequence available is given in the table below, which is
based on the data in H & H.
| m |
n |
Length |
| 5 |
3 |
31 |
| 6 |
5 |
63 |
| 7 |
6 |
127 |
| 9 |
5 |
511 |
| 10 |
7 |
1023 etc |
Want to find out more about VHDL? Check out this
URL, where you can access an on-line course covering the basics (caution, this
involves a largish download) ...
- One approach: cut and paste into your favourite editing package.
This may be quite handy if you need to import parts of the text into your
own computer for writing reports;
- The 'export' technique. This is also quite quick and produces a
plain text file which can be exported.
With the source window active give the command File > Export > To
File
When prompted, enter the name of a text file. For consistency, you may
wish to use [design-name].txt.
This will be created in your cbt directory hierarchy.
You can now print using Unix commands from an xterm shell, for example: lp
-dljmr1 ring_vhdl.txt
- The 'Mentor' approach: this should work, but was troublesome in 2003 -
details are given for completeness.
With the source window active give the command File >
Print.
When prompted, enter mgcps_a4 as the
printer.
Open an xterm shell and run the utility: mgcplot to process the print
output .
Reply N to the three initial prompts.
Your listing should be in a Postscript 'document' file which you can select by number.
Select Option (1) to preview on the screen using Ghostview.
Use Ghostview's Print option to send the Preview image to your chosen Teaching System
printer (e.g. ljmr1).
The use of mgcplot is also described in Lab Guides 2, 3 and elsewhere.
Problems visualising the structure of the MOS transistor?
If you are experiencing difficulty in appreciating how the layout diagrams map onto the
3D structure of the MOSFET, you may like to try out our new Java-based visualisation tool.
This offers a 3D view of a MOSFET showing its structure, and uses the same colour
codes as used in (most) layout packages. You can also see descriptions of layer
names and SEM images of real device features for comparison.
This work is the result of a 4th year M Eng project carried out by Amr Monawir, who now
works at Xilinx. To access it, click the icon
below; the Java applet should open in a new window:-
3D Model of a
MOS transistor
Other
applets for MOS transistors
Design a fast gate!
For the layout/verification section, Labs 7 and 8, remember we are seeking to try and
make as fast a NOR2 gate as we reasonably can. You should do what you can in the
layout to keep parasitic capacitances to substrate as low as possible.
Can't find models for TR_N/TR_P
In Lab 7, be sure to follow the instructions for creating a viewpoint for Accusim with
some care. In connection with this, we have on fairly rare occasions encountered a
problem in which Accusim gives the error message:- 'Can't find models for
TR_N/TR_P'. You may not meet this problem, but if you do, ask a demonstrator or
contact us by email (mentor1) without delay.
Strange colours afflict ICgraph display after using Netscape
Navigator or after print preview
It appears that Netscape (when run on the Teaching System) sometimes interacts
adversely with some graphical displays, giving (for example) purple text on a black
background. Until we can ascertain if there is a fix for this, you may wish to
avoid using Netscape on the Teaching System when logged in as mentorxx -
use the local browser on the PC instead. Otherwise, use Netscape to check the page,
then close it down before starting up Mentor. You can always re-open it later, for
example, by using the popup menu option on the RH mouse button (click RH mouse button with
cursor over fvwm desktop).
In Lab 8, we have occasionally noticed an adverse interaction between ICgraph
and ghostview, the graphical viewer used to preview and print layout
plots. This manifests itself as follows:-
- Use File > Print > Print Cell to print a cell to a temporary file
- Run mgcplot in an xterm shell to preview/print the
file (this makes use of ghostview)
- On return to ICgraph the colour palette settings appear corrupted
This problem does not appear consistently, and it is possible it occurs only at the
first use of ghostview.
We have no complete solution to this, other than to exit and restart your ICgraph
session. We recommend you leave preview/printing until your design work is complete
and the design saved.
No printable files visible in mgcplot
In Mentor applications run on the Teaching System, printing or plotting involves two
stages. Typically, you use the Print feature in Design Architect, ICgraph, QuickSim
II, Accusim or one of the other Mentor applications, and specify the printer device as mgcps_a4.
This prepares the output for a monochrome Postscript A4 printer but does not
actually send the output to a printer. The mgcplot utility is
provided to control the final printing operation. When you run mgcplot,
you should see something like the following:-
tw400% mgcplot
Processing files in /export/mgcC4/tmp for group mentor1.
Do you want to process A4 colour postscript output [N]? N
Do you want to process A4 HPGL2 output (no preview available) [N]? N
Do you want to process A3 postscript output [N]? N
These are the mentor files that you have created.
1) va211.sheet1.1
2) quit
Choose a file or quit
Note that your UID will appear in the file name in place of va211.
The keyword sheet1 normally refers to a sheet created by Design
Architect. The final 1 gives a serial number to distinguish this
file from other prints you may have created.
The symptoms of the problem are that on executing mgcplot no files are
seen, for example:-
...
These are the mentor files that you have created.
1) quit
Choose a file or quit
Possible causes:-
- Check carefully that you entered a valid printer device in the Print dialogue of the
Mentor application. You cannot enter the name of a Department
printer (e.g. ljmr1) here. In the early stages of the project, only
the code mgcps_a4 is valid. In the final week of the project,
printer code mgcpsa4_colour (and possibly others) will become available.
- Maybe you logged out since creating the print output and now wish to print an extra copy
by running mgcplot. Check that you have logged in to the same
server as you used to create the print output. The print output is stored in a
special temporary directory only accessible on that server. Hence, for example,
using the Design Architect Print command while logged in to tw600, then
logging out, and later logging in to tw300 to run mgcplot
will not work! You must run mgcplot from tw600
in this instance.
Colour plots appear as black and white only
The symptoms are that under Preview using Ghostview the plot is
entirely black & white.
Check that you chose a printer that supports colour in MGC > Setup Printer.
The standard choice is mgcpsa4_colour.
Colour plots appear as black and white with occasional
parts in colour
There is an adverse interaction between XWin-32 and ICgraph which
under certain circumstances interferes with generation of colour postscript output.
The symptoms are that under Preview using Ghostview the plot is
largely in black & white. Occasional parts may be in colour (often red
polysilicon).
To fix this you must ensure that your XWin-32 session is set to pseudocolor
support. Left click the System button (at extreme left of XWin-32 title
bar); select Xutil-32 and then choose the Colours Option.
Each mouse click on this option toggles its state between On and Off. Make
sure this option is checked. In Hummingbird eXceed, use System
> Tools > Configuration and choose Video. Check that
Server Visual is set to Pseudocolor. If you change
this parameter a restart of eXceed may be necessary.
Creating a hierarchical layout for
your design (Lab Guide 8)
In 2005 the following is no longer relevant, since we are this year using a
more recent version of Mentor, ICFlow 2003.3.
We have become aware of some unusual features of Mentor C.4 (the version in
use with the VLSI project) that particularly affect those parts of Lab 8 concerning
the hierarchical layout. Producing a flattened layout is not affected. The
symptoms are as follows:-
- When you try to promote the cell to CBC mode, that option is greyed out.
- The Library Edit dialogue does not appear to add new cells to the ringlib library.
- In the hierarchical layout, automatic routing cannot be completed.
These effects are specific to C.4. More recent versions do not exhibit these
problems. The causes of the problems mentioned and the workarounds we have
introduced are summarised
below.
- Mentor C.4 creates cells by default in CBC mode. Promoting to CBC is therefore not
necessary once the Rule set has been defined, and ICgraph 'greys out' the option,
meaning that it is unavailable.
- There appears to be a bug in the Library Edit dialogue which means that selected cells
are not displayed in the List Box. Also, there are problems when the cells come from
different sources. You need to load cells from two sources: the Mietec CMOS24 cell
library, and your own cbt directory. One workaround is to use the (menu
bar) > File > Library > Add to Library .. command, but this is tedious
as it will only let you add one cell at a time. The most satisfactory solution is to
use a work-around procedure to force the dialogue to display the cells, and to use the
dialogue twice, once for each of the two library sources.
This is described in Lab Guide 8.
- In the hierarchical design, a modified procedure and some special userware (to
eliminate unwanted port references) are needed to allow the automatic routing
to be completed, because of the way this release of Mentor handles pads and
ports. The necessary userware script delete_unplaced_ports.ample has been placed in each
user's cbt directory and its use is described in the lab
guide.
Accessing Mentor from outside CUED
A number of users are taking advantage of college computers or possibly personal
machines to access Mentor outside the scheduled sessions. We will give what help we
can with this, but it is a non-trivial exercise, and there is a risk you will spend more
time tweaking software than designing your chip!
Here is a recipe that has been found to work with Hummingbird Vista eXceed
Version 6.0 ...
- Set your PC up in 256 colour screen mode. 65K (HiColor) and some other modes won't
work with Mentor.
- Set the Communication Mode to XDMCP-query, and in the Configure (XDMCP
Startup Modes) box, put the host you want to connect to e.g. tw400.eng.cam.ac.uk
- You may have to set up a Font Server in the Configuration program.
If so, the following settings should work:-
Transport = tcp
Server = tw900.eng.cam.ac.uk
Port = 7100
Status = Load
- Set Single Window mode from the Configuration program
- You will probably have to login to the Teaching System using your usual account and ID,
e.g. 96xyz
- When you have done this, give commands as follows:-
- rlogin twB -l YourUID
where twB is the server you require; -l is 'minus ell' and YourUID is your own
UID. You will have to give your password at this point.
- export DISPLAY=ip.address:0
where ip.address is the IP address of the machine
on which you are working, and :0 is 'colon zero'
If you don't know your IP address, look for a utility called winipcfg.exe
in your \Windows directory. Run this to tell you the current IP address being used.
Alternatively, you may be able to use the machine name, e.g. export DISPLAY=pc09.college.cam.ac.uk:0
- cd /usersG/ptiivlsi/mentorXX
where mentorXX is the name of your Mentor workspace.
- . mentor_start_env
- mentor
- Be patient! With all the network traffic that is involved, running Mentor in this
way is sloooow!
- Read the caveats below about Accusim and Bold Browser
- Let us know if you find alternative arrangements that work for you.
Notes
- We have noticed problems with the PC-based X clients (Xwin, eXceed) we have available to
us, in certain parts of Accusim, particularly charting transient responses. This
does not appear to be a Mentor problem, since it works fine with the xterms and fvwm
window manager on the HP, and appears to be a limitation of some editions of the PC-based
X clients. If your X client is more up to date, you may not encounter this
problem.
- With Xwin, you should avoid using HiColour modes (16 bit/65536 colours) and probably
24-bit colour modes in your display setup. These cause a crash (often 'Out of
Memory') when Mentor starts up. Some X clients have menu options to limit the number
of colours supported under X, and this may help.
- There is a known bug with certain releases of Vista eXceed (version 5.0 and certain
others) in which Bold Browser displays are distorted and unreadable. We are not
aware of any fix for this. If you find one, please let us know! This year
(2005) this should not be a problem since the Bold Browser is not used in
the current release of Mentor: an Acrobat-based Help System is available
instead.
- Certain commands, notably those that make use of the function keys in combination with
the mouse, may not work. There are occasional problems with mapping of keys such as Tab
and Delete. You may find other examples of scripts in your ~/bin
directory, e.g. mentorHP - if not, and you thin, you need
one, enquire of a demonstrator. The script mentor has
proved to work with a number of PC-based X clients; however there is no guarantee that it
will work with yours, and you may have to create your own!
Page created by David Holburn
Monday, 15 May 2006
