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Aberration determination and compensation in high resolution transmission electron microscopy
The main area addressed by this dissertation is the accurate measurement of the Transmission Electron Microscope (TEM) aberrations present in the objective lens. These measurements allow correct adjustment of the TEM which should improve the throughput of the microscope without so much dependence on highly skilled operators. They also provide precise information about imaging conditions essential for resolution improvement through image reconstruction. Various techniques are described which can be used to determine TEM aberrations. Out of all these, the measurement of image shifts and diffractograms (power spectra) for various predetermined injected beam tilts hold most promise. It has proved possible to automate the measurement of image shifts; this however needs special filtering techniques at high resolution which are explored at length.
A number of large image data sets were collected to test the current imaging models critically. Serious discrepancies between predicted and actual data observations were found to be well accounted for by a hitherto neglected aberration, three-fold astigmatism. This aberration was found to be present at levels that cause serious image degradation and its value has been determined for one particular microscope. Reconstruction methods are reviewed. The aberration determination methods developed have made viable for the first time a reconstruction method based on multiple beam tilt images which achieves close to a doubling of resolution. Some experimental results from the use of this approach are presented.
Timing verification in digital CMOS VLSI design
The dissertation describes an investigation into timing verification in digital CMOS VLSI design. Timing verification plays a very important role in the computer-aided design of integrated circuits. For many years, much effort has been focused on verification of logic correctness in the system. However, practical experience suggests that a logically correct circuit may fail to operate as specified, owing to hazards, clock skews, unexpected long delays, etc. The purpose of timing verification is therefore to anticipate these timing errors in the system. Hitherto, such activities have usually been pursued separately from the circuit design and layout process. As VLSI systems grow more and more complicated, it has become clear that the issue of timing verification must also be regarded as an essential step in the design procedure, in addition to consideration of the timing constraints imposed by the performance specification.
Conventionally, timing verification includes both timing simulation and timing analysis, which can be carried out respectively through delay modeling for the devices used, and by searching for critical paths in the system. Existing techniques of delay modeling may be categorized as numerical modeling, macromodeling and RC modeling. Traditional techniques for timing analysis feature summing up the delays along selected signal paths in nature. They either are computationally time-consuming or produce inaccurate results.
Two main themes constitute this dissertation. Firstly, a theory of semi-analytic delay modeling for MOS circuits has been established, in an attempt to achieve accurate delay estimates without exhaustive numerical iteration. The model utilises a series of analytic functions to calculate the delay time based on a classification of the combined effect of the input slope, the size of transistors and the output driving capacity. Therefore it is suitable for dealing with timing verification problems in VLSI, and also provides a theoretical basis for circuit performance optimization. Secondly, the hierarchical properties inherent in VLSI designs are exploited and characterized, so that the maximum and minimum delays of whole system can be decomposed into those of each block under certain specific rules. In this way, path evaluation is confined only to local portions of the circuit, resulting in great efficiency in the algorithm. In order to test the novel approaches introduced in the dissertation, a timing verification program MOTIVE has been developed and successfully run on several practical circuit designs. The results imply that a significant improvement has been obtained in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.
Knowledge-based engineering for the Scanning Electron Microscope
Nicholas Hugh Mullen Caldwell
The dissertation is an account of the authors research into the analysis, design, and implementation of knowledge-based (expert) systems for applications in the field of scanning electron microscopy. The specific tasks of interest have been fault diagnosis and instrument control. This research represents the first utilisation of knowledge-based techniques within electron microscopy.
The dissertation begins by providing background material on the scanning electron microscope and surveying the expert systems literature with regard to critical areas of system design. The target applications and the associated research objectives are next summarised.
A set of novel algorithms for improving the microscope by enhanced automatic control of fundamental instrument parameters, namely tungsten filament saturation and alignment, are presented, and the area of automatic focus algorithms is reinvestigated. Research into the design and implementation of an expert system for microscope fault diagnosis, including mechanisms for interfacing the expert system to the Internet, is discussed. This is followed by a detailed presentation of the development of a knowledge-based approach to instrument control.
The next segment of the dissertation concentrates upon theoretical issues arising from the preceding work. A proposal is made to classify network-aware expert systems, and the impact of the Internet and the World Wide Web upon such systems is discussed within this context. An analysis of the work is performed to indicate how the practical portions of the research may be generalised to other tasks within scanning electron microscopy and outwith to other scientific instruments.
Finally the results of the work are evaluated with respect to the research objectives. A set of appendices and a full bibliography conclude the dissertation.
Real-time analysis of fetal phonography signals
Timothy Dominic Rowsell
This programme of research investigates computerised methods to provide objective metrics of human fetal heart activity in real time through analysis of the vibrations of the maternal abdomen that result from the fetal heart beat.
A low-cost hardware platform is used for computer algorithm development and implementation. This consists of an IBM PC compatible computer fitted with a digital signal processor card to enhance the computational performance.
There is an extensive body of knowledge relating fetal health to the fetal heart rate. To provide an interface to this an algorithm to estimate the mean fetal heart rate from fetal heart sound recordings is developed. This utilises auto-regressive spectral estimation. The algorithm is implemented to execute faster than real time and provides consistent results even when appl ied to heart sound signals of widely differing quality.
The beat-to-beat fetal heart rate and systolic intervals can be estimated from the instants of occurrence of the principal heart sounds. This prompts an investigation into the characterisation of hear t sounds. The findings are incorporated into an algorithm for heart sound recognition. When tested on fetal heart sound recordings obtained from five pregnancies, the estimated mean success rate in fetal heart sound identification is 95% for first heart s ounds and 44% for second heart sounds.
Using beat-to-beat heart rate estimates obtained using from the heart sound identification algorithm, the heart rate variability estimated between successively identified first and second heart sounds is compared.
fetal distress, fetal asphyxia, fetal phonography, fetal phonocardiography, fetal heart sounds, fetal heart rate, systolic intervals, digital signal processing, antepartum fetal monitoring
Submitted for consideration by the University of Cambridge for the degree of Doctor of Philosophy May 1993
Knowledge-Based Engineering for the Scanning Electron Microscope
Nicholas H M Caldwell
Submitted for consideration by the University of Cambridge for the degree of Doctor of Philosophy November 1998
Application of VLSI to wireless networks
Vinod Aravindakshan Lalithambika
This dissertation investigates the feasibility of implementation of an integrated optical wireless receiver array using a standard CMOS fabrication process. The project arose from a partnership formed between the University of Cambridge the University of Oxford, the Imperial College of Science and Technology in London, and the University of Huddersfield to develop a range of integrated components for use in an indoor optical wireless network (OPTWIRE).
The research described in this dissertation paves the way for a completely integrated receiver array to be used with OPTWIRE. The aim was to design an optical wireless receiver array for data rates in excess of 100Mb/s, a rate sufficiently fast to support real-time video applications. A transimpedance amplifier, which consists of a voltage amplifier with resistive feedback, is used as the first stage. Development of a CMOS transimpedance amplifier required optimisation for high input capacitances typical of the large photo-detectors required for indoor optical wireless applications. High gain is essential to obtain good performance and this may be obtained through the use of multiple stages. The design has been optimised for maximum gain. To assist in the detailed design and to allow the sensitivity of the performance to key parameters to be visualised graphically, a nomograph was developed. The contours of the nomograph show how the DC bias, the pole frequency, and the gain vary with the sizing of transistors. In addition the input transistors were sized to achieve low noise while taking into account the high source capacitance. The theoretical design was verified by fabrication of an integrated preamplifier realised in the Alcatel CMOS 0.7um process. The measurement results presented show that the preamplifier is able to achieve the required bitrates of 310Mb/s (155Mb/s Manchester coded) for an input capacitance of 10pF.
Imaging receiver arrays are a promising means to improve the performance of infrared wireless links. The use of diversity signal processing can reduce ambient light noise and receiver thermal noise, enabling higher bit rates to be achieved with reduced transmitter power. An architecture for an optical wireless receiver array is presented. This design includes three preamplifier channels based on the transimpedance amplifier already developed, and includes a selector-combiner circuit that implements equal gain combining (EGC) and select best (SB) detection techniques. The receiver array is able to achieve bit rates up to 310Mb/s. Features that allow for position detection and tracking of the transceivers in a mobile environment are demonstrated. Measurements carried out on a CMOS receiver array chip, realised in Alcatel CMOS 0.7um process, indicate the feasibility of a fully integrated CMOS receiver array.
Submitted for consideration by the University of Cambridge for the degree of Doctor of Philosophy April 2002
Integrated Circuit Design for Wireless Network Receivers
Valencia M Joyner
With the proliferation of mobile devices over the past decade, wireless technology is rapidly evolving as a key area of research and product development. Wireless links based on optical transmission are emerging as a viable technology for their potential to overcome the communication bandwidth bottleneck between high-speed fibre backbone networks and the end user. Optical transmission offers several advantages over RF in terms of connection speed, networking security and unregulated bandwidths in the THz range. The ability to fabricate low-cost transceiver components is a key requirement to the development of optical wireless links into a commercially viable technology. To investigate and address the challenges of optical wireless technology, a number of UK universities have been involved in a project to demonstrate the feasibility of integrated optical transceiver components that can provide indoor line-of-sight (LOS) communication at 310Mb/s and beyond.
This thesis presents several circuit components and techniques to enable the realisation of' fully integrated receivers for use in LOS optical wireless links operating at 310Mb/s, 1Gb/s and beyond. It is shown that imaging diversity receivers based on detector arrays mounted oil the supporting CMOS electronics can be used to enhance the optical link performance in LOS systems. To improve data recovery from the detector array, a novel selection and combination approach is introduced to implement well-known diversity combining methods. A selector-combiner circuit has been designed and developed in CMOS to allow the arbitrary combination of signals and support diversity combining techniques. This circuit has been realised in a 0.7um CMOS process and tested on-chip in a 3-pixel diversity receiver demonstration operating at 310Mb/s.
In order to fully exploit the bandwidth capabilities of optical signals, this thesis investigates the realisation of integrated receivers ill CMOS operating at 1Gb/s. A theoretical background is presented on the design of front-end preamplifier circuits in CMOS operating at the target speed and driven by detectors with a large aperture (and large capacitance); such devices are commonly used in optical wireless links to provide adequate receiver field-of-view. Transimpedance amplifiers with both the traditional common-source and common-gate input stages have been analysed and compared in terms of gain, power dissipation and noise performance. The most comprehensive discussion to date is presented of the relative merits of each configuration when implemented in a standard CMOS process, driven by a photodetector with a capacitance of 6pF and operating at a bit rate of 1Gb/s. A common-source and common-gate preamplifier circuit have been designed and fabricated in a 0.35um CMOS process. The common-source preamplifier circuit achieves a gain of 44.6dB, -3dB bandwidth of 500MHz, and an input-referred current noise PSD of 14.8pA/root Hz; good eye openings have been demonstrated at bit rates up to 1Gb/s. The common-gate preamplifier circuit achieves a gain of 44dB, -3dB bandwidth of 481MHz, and an input-referred current noise PSD of 22.4pA/root Hz; good eye openings have been demonstrated at bit rates up to 700Mb/s.
Flip-chip packaging is a key technology enabling low cost integration of high performance detector arrays directly to the supporting CMOS circuits with low parasitics. This technology enables significant improvements to the design and implementation of scalable optical receiver arrays. To conclude, this thesis presents the design and fabrication of a 7-pixel, flip-chip compatible CMOS receiver. This receiver has been developed for flip-chip attachment to a detector array that will be used in a free-space optical link demonstrator operating at 310Mb/s.
Submitted for consideration by the University of Cambridge for the degree of Doctor of Philosophy July 2003
Integrated Circuit Design for Wireless Network Transmitters
Rina J Samsudin
In this thesis, the development of a novel, fully-integrated pulse-shaping LED driver is pursued. The driver is designed for 310Mb/s operation with driving capabilities suited to 980nm resonant-cavity light-emitting diodes (RCLEDs), and is to be incorporated in an indoor optical wireless system prototype in further research. The driver designs are implemented in 0.7mm and 0.35mm commodity mixed-signal CMOS processes. The novel driver circuit employs current-steering methods to reduce supply and ground bounce by maintaining constant current operation. It comprises five parts: (1) digital voltage-to-current transducer (modulation circuit), (2) dummy modulation circuit, (3) bias circuit, (4) charge injection circuit and (5) charge extraction circuit. The latter two use original timing generators that produce edge-triggered current spikes at different instances of the output current pulse to reduce optical transition times of the LED. Additional pulse-shaping capabilities are that current amplitudes and injection/ extraction pulse widths can be adjusted in real time using external voltage controls. These features offer added flexibility, in the sense that the driver output can be tailored, to some degree, to drive different types of light sources. Much of the design and layout work was conducted using Mentor Graphics software. Analogue simulations were conducted using BSIM level 53 models to predict circuit behaviour and performance variations due to corner parameters. For simulation purposes, a circuit equivalent model of the target RCLED was developed in order to emulate the electrical response of a typical device. In order to evaluate the driver experimentally, a series of integrated circuits (ICs) were fabricated and test kits were constructed. Layout techniques suitable for high-speed, high-current transistors and interconnects were implemented to reduce electromigration and distributed effects. Results from electrical and optical tests showing 310Mb/s operation and pulse-shaping capabilities are presented. Tests were conducted using RCLEDs and commercial lasers, demonstrating driver compatibility with different emitters. Driver performance is limited by packaging effects due to the large operational drive currents. The driver shows tremendous promise – simulations show that the inherent bit rate capability is much higher than 310Mb/s. This gigabit potential can be achieved provided better packaging methods are used. Further methods to improve parasitic robustness using circuit techniques are proposed.
Submitted for consideration by the University of Cambridge for the degree of Doctor of Philosophy July 2003
Autofocusing and Astigmatism Correction in the Scanning Electron Microscope
Chris F Batten
This work investigates both the theoretical and practical aspects of autofocus- and astigmatism correction in the scanning electron microscope A general framework is used to divide the problem into four primary areas of concern: noise reduction, regions of interest, sharpness measures and maximum sharpness search algorithms. Each of these areas is investigated in detail and several novel concepts are introduced including: the use of reduced domain median filters to mitigate limited bandwidth distortion, a method for confining the region of interest to specimen features, more sophisticated maximum sharpness search algorithms such as the variable stepsize search and the Fibonacci search, and interpolation based on a model of variance as a function of defocus.
A development testbed was established which allowed for rapid prototyping in MATLAB, implementation in Visual C++, and then final packaging as an ActiveX control. The theoretical work was implernented in a rnodular component (called SEMimage) for use with the Leo 440 SEM located in the Scientific Imaging Group at the Cambridge University Department. The framework was used to develop algorithms for full autofocusing, fine autofocusing, real-time autofocusing, and astigmatism correction. Real-time autofocusing enables the software to automatically determine when an image has become defocused and to then take appropriate action to move the image back into focus. Real-time beam alignment and signal to noise calculation were also implemented.
SEMimage was tested on the instrument and provided an effective means for automated focusing and astigmatism correction. The fine autofocusing provided by SEMimage is relatively fast and accurate, and the real-time autofocusing provides a unique method for keeping the instrument in focus.
Integrated Circuit Design for Wireless Networks
Fu- Chuan Lin
Submitted for consideration by the University of Cambridge for the degree of Doctor of Philosophy December 2005
Autofocusing and Astigmatism Correction in the Scanning Electron Microscope
Geoffrey C Martin
Submitted for consideration by the University of Cambridge for the degree of Doctor of Philosophy September 2007
Design and Development of a Heterogeneous Hardware Search Accelerator
Shawn S N Tan
Submitted for consideration by the University of Cambridge for the degree of Doctor of Philosophy February 2010
Design and Analysis of High Linearity Circuits for Wireless Receivers
Submitted for consideration by the University of Cambridge for the degree of Doctor of Philosophy May 2010