A Closely Integrated Reconfigurable Image Capture System and Its Applications

David Jordan and David Holburn

Department of Engineering

University of Cambridge, UK


Keywords

Image Capture, Subpixel Resolution

Abstract

A modular image capture system with close integration to CCD cameras has been developed. The aim is to produce a system in which the CCD sensor, image capture and image processing are integrated into a single compact and reconfigurable unit. This gives a number of advantages over conventional image processing systems. The close integration of CCD sensor and framestore provides a direct mapping between CCD sensor pixels and digital image pixels in the framestore memory. This one to one mapping has a direct benefit for measurement applications. Other advantages include possible closed loop control of image acquisition and sensor parameters, reduction of output data bandwidth by local image processing and analysis, and easy installation due to compactness. The CCD sensor resolution, timings and scanning are not restricted by the need to produce a standard video signal with its defined, fixed parameters. A compact form of the image capture system is being developed using just two chips. This is being integrated with a miniature PC processing unit using a novel modular, demountable interconnection system to provide a complete reconfigurable image capture and processing system in a single compact unit.


Block Diagram of System

The prototype system demonstrates the ideas of the closely integrated digital image capture system. In addition to the close linking of CCD sensor, it was designed to be modular and expandable, with the capability of supporting different sensor sizes. This allows the system to meet the requirements of a general purpose system by being configurable to meet the needs of specific applications. The system has been interfaced to a Motorola 56000 digital signal processor board to provide the processing unit for image analysis and processing. It has been shown to operate satisfactorily with a number of different CCD cameras formats, capturing images of up to 512 by 512 by 8 bit pixels over a range of pixel rates. The digital signal processor board is interfaced to a PC for the development and control of image processing tasks. The system is currently being used for the investigation of algorithms for measurement to subpixel resolutions. Applications for a unit capable of measuring to subpixel resolution include manufacturing quality control, automated parts inspection and dimension checking.

With the one to one mapping of camera pixels to framestore memory locations, it is possible to perform measurements of greater accuracy than a single pixel (subpixel resolution). To determine the response of the camera to an edge moving across the field of view, a set of images was captured as a well defined edge was accurately stepped across the field of view. This set of images is used as the input to a number of different subpixel resolution algorithms. The results are compared with measurements of the edge position as the images were captured and with the results from the other algorithms.

The algorithms being compared include those based on interpolation, spatial moment, grey level moment and centroiding operations. Interpolation generates values between the discrete pixel values which can be analysed for edges at subpixel resolutions. The moment based operators locate an edge to subpixel positions in one dimension. The algorithms find the ideal edge which matches the first three moments of the sample data for a given window size. The nth order grey level moment is defined as the sum of the nth power of the grey level values. The nth order spatial moment is defined is defined as the sum of the grey level value multiplied by the nth power of the distance of the pixel from the window origin. The centroiding operations determine the position of the centroid of an object to subpixel resolutions. Other methods include finding the local maxima and minima of differential operators.

A highly compact form of the image capture system is in an advanced stage of development. This consists of a single FPGA device and a single VRAM providing a two chip image capturing system capable of being integrated with an analogue to digital conversion stage into a CCD camera. The redesigned system can capture images of up to 1024 by 1024 by 16 bit pixels.

As part of a separate development, a miniature embedded PC has been developed using a novel modular interconnection technique. The interconnection technique consists of two components; a carrier for VLSI circuits and a connector to interconnect the VLSI carriers. A system consists of a number of carriers and connectors stack together in a tower-like structure. The connectors may be easily taken apart and either additional carriers added or new carriers substituted. This allows the system to be reconfigured for different applications and to be upgraded to take advantage of technological advances without the need to redesign the whole system. Only that part of the system being updated needs to be redesigned. The miniature PC consists of five different carriers and provides a processing unit in a three dimensional format highly suited to integration into a CCD camera unit.


Diagram of PC Tower

Work is under way to interface the compact capture system to the PC using this interconnection technique, combining CCD sensor, image capture and image processing into a single demountable compact unit.


Presented at Sixth International Conference on Image Processing and Its Applications, Dublin, Ireland, July 1997

IEE Conference Publication No.443 Volume 1 Pages 156-160


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Last updated Monday 15th September 1997 by
dsj@eng.cam.ac.uk